Subclass of CIM_Controller
PCIController is a superclass for the PCIBridge and PCIDevice classes. These classes model adapters and bridges on a PCI bus. The properties in PCIController and its subclasses are defined in the various PCI Specifications that are published by the PCI SIG.
Defines the PCI interrupt request pin (INTA# to INTD#) to which a PCI functional device is connected.
ValueMap Values 0 None 1 INTA# 2 INTB# 3 INTC# 4 INTD# 5 Unknown
An array of integers that indicates controller capabilities. Information such as “Supports 66MHz” (value=2) is specified in this property. The data in the Capabilities array is gathered from the PCI Status Register and the PCI Capabilities List as defined in the PCI Specification.
ValueMap Values 0 Unknown 1 Other 2 Supports 66MHz 3 Supports User Definable Features 4 Supports Fast Back-to-Back Transactions 5 PCI-X Capable 6 PCI Power Management Supported 7 Message Signaled Interrupts Supported 8 Parity Error Recovery Capable 9 AGP Supported 10 Vital Product Data Supported 11 Provides Slot Identification 12 Hot Swap Supported 13 Supports PCIe 14 Supports PCIe Gen 2 15 Supports PCIe Gen 3 16..32767 DMTF Reserved 32768..65535 Vendor Reserved
Reports if the PCI device can perform the self-test function. Returns bit 7 of the BIST register as a Boolean.
Defines the minimum amount of time, in PCI clock cycles, that the bus master can retain ownership of the bus.
The slowest device-select timing for a target device.
ValueMap Values 0 Unknown 1 Other 2 Fast 3 Medium 4 Slow 5 Reserved
Current contents of the register that provides basic control over the ability of the device to respond to or perform PCI accesses.
An array of free-form strings that provides more detailed explanations for any of the PCIController features that are indicated in the Capabilities array. Note, each entry of this array is related to the entry in the Capabilities array that is located at the same index.
Doubleword Expansion ROM-base memory address.
Specifies the system cache line size in doubleword increments (for example, a 486-based system would store the value 04h, indicating a cache line size of four doublewords.
Register of 8 bits that identifies the basic function of the PCI device. This property is only the upper byte (offset 0Bh) of the 3-byte ClassCode field. Note that the ValueMap array of the property specifies the decimal representation of this information.
ValueMap Values 0 Pre 2.0 1 Mass Storage 2 Network 3 Display 4 Multimedia 5 Memory 6 Bridge 7 Simple Communications 8 Base Peripheral 9 Input 10 Docking Station 11 Processor 12 Serial Bus 13 Wireless 14 Intelligent I/O 15 Satellite Communication 16 Encryption/Decryption 17 Data Acquisition and Signal Processing 18..254 PCI Reserved 255 Other
uint8 BISTExecution ()
Method to invoke PCI device self-test. This method sets bit 6 of the BIST register. The return result is the lower 4 bits of the BIST register where 0 indicates success and non-zero is a device-dependent failure. Support for this method is optional in the PCI Specification.